Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device having a metal resistive element layer.
Description of the Background Art
Conventionally, a microcomputer product and an oscillator are different in structure, but recently, by incorporating the oscillator in a microcomputer chip, a layout area has become small and the cost has been reduced, and the like. In the case where the oscillator is incorporated in the microcomputer chip, it is necessary to output a stable oscillation frequency in various environments (such as voltage and temperature), so that as for a high-speed OCO (On Chip Oscillator) circuit of the microcomputer product, it is required to attain 40 MHz±1% as target precision.
Here, as a resistor of a constant-current generation circuit in the high-speed OCO (On Chip Oscillator) circuit serving as an analog circuit, a polysilicon resistor is used. However, as for the polysilicon resistor, its resistance value is fluctuated by a stress due to a piezo resistance effect. Especially, the resistance value is considerably fluctuated due to a mold stress that occurs in a packaging step or thereafter. Thus, a frequency of the high-speed OCO circuit is largely fluctuated, which could make it difficult to attain the target precision of the high-speed OCO.
The high-speed OCO circuit in the microcomputer product is normally formed to have a multilayer wiring structure, and the resistor is mostly formed on a uppermost layer of the multilayer wiring structure. Therefore, an upper face of the resistor is directly covered with a protective film, and it is likely to receive a stress from the protective film. With a view to suppressing a variation in resistance value due to the stress from the protective film, a technique in which the resistor is formed on the layer under the uppermost layer of the multilayer wiring structure has been disclosed in Japanese Patent Laying-Open No. 2001-267320, Japanese Patent Laying-Open No. 2011-155192, and Japanese Patent Laying-Open No. 2008-130918.
According to Japanese Patent Laying-Open No. 2001-267320, a wiring layer and a resistor are electrically connected through a conductive layer (buried contact hole) extending from the wiring layer positioned above the resistor to the resistor. Meanwhile, according to Japanese Patent Laying-Open No. 2011-155192, a resistor and a wiring layer positioned below the resistor are electrically connected through a conductive layer (contact plug) extending downward from the resistor.
However, Japanese Patent Laying-Open No. 2001-267320 and Japanese Patent Laying-Open No. 2011-155192, and Japanese Patent Laying-Open No. 2008-130918 in which an electrical connection is not made by the conductive layer do not disclose an idea that simultaneously forms, with the same mask, a conductive layer to be electrically connected to the resistor formed on the layer lower than the uppermost layer, and a conductive layer to connect the wiring layers that are not the resistor. Thus, as long as there is no idea that simultaneously forms the conductive layer for the resistor, and the conductive layer for the wiring layers that are not the resistor, with the same mask, there is a need to form the conductive layer for the resistor and the conductive layer for the wiring layers that are not the resistors, with different masks, which could considerably complicate the step, and increase the manufacturing cost.
The other problems and new characteristics will become more apparent from the description in this specification and the accompanying drawings.